----------------------------------------------------------- address = $8000 name = LEDG_SW read fedcba9876543210 SSSSSSSSSSSSSSSS S = switches on DE2-115 write fedcba9876543210 -------GGGGGGGGG G = LED Green ('1' is ON) ----------------------------------------------------------- address = $8001 name = LEDR read fedcba9876543210 --------------ME M = '1' if running in modelsim E = '1' if running in emulator write fedcba9876543210 -------RRRRRRRRR R = LED Red ('1' is ON) ----------------------------------------------------------- address = $8002 - $8005 name = 7SEG read fedcba9876543210 2 ---------------- 3 ---------------- 4 ---------------- 5 ---------------- write fedcba9876543210 2 -6543210-6543210 3 -6543210-6543210 4 -6543210-6543210 5 -6543210-6543210 -6543210-6543210 = Hex Segment of Hex 1 / 0 ('1' is ON) -6543210-6543210 = Hex Segment of Hex 3 / 2 ('1' is ON) -6543210-6543210 = Hex Segment of Hex 4 / 4 ('1' is ON) -6543210-6543210 = Hex Segment of Hex 5 / 6 ('1' is ON) ----------------------------------------------------------- address = $8006 - $8007 name = LCD read fedcba9876543210 6 -------BDDDDDDDD 7 ---------------- B = '1' if read/write request is busy D = Data after request note: wait 1 cycle after read/write request before read write fedcba9876543210 6 ------WRDDDDDDDD 7 ---------------- W = '0' is request write, '1' is request read R = LCS RS D = data to write ----------------------------------------------------------- address = $8008 - $8009 name = IRQ read fedcba9876543210 8 -----------HADTT IRQ MSK 9 -----------HADTT IRQ MEMORY TT = Timer 2/1 IRQ D = Audio DAC FIFO run low A = Audio ADC FIFO run full H = HCORE has data write fedcba9876543210 8 -----------HADTT IRQ MSK 9 -----------HADTT IRQ MEMORY TT = Timer 2/1 IRQ D = Audio DAC FIFO run low A = Audio ADC FIFO run full H = HCORE has data description: IRQ MSK is used to enable given interrupts (for example D = '1' then Audio DAC irq will be used) IRQ MEMORY reflect after interrupt which interrupt is the source (for example TT = '01' then Timer 1 made this interrupt) You should/have to clear the given interrupt bit in IRQ MEMORY before leaving interrupt service routine. ----------------------------------------------------------- address = $800A - $800F name = TIMERS read fedcba9876543210 A DDDDDDDDDDDDDDDD Timer 1 low B DDDDDDDDDDDDDDDD Timer 1 high C ---------------- D DDDDDDDDDDDDDDDD Timer 2 low E DDDDDDDDDDDDDDDD Timer 2 high F ---------------- write fedcba9876543210 A DDDDDDDDDDDDDDDD Timer 1 low (set before timer 1 high) B DDDDDDDDDDDDDDDD Timer 1 high C ------------CLSR D DDDDDDDDDDDDDDDD Timer 2 low (set before timer 2 high) E DDDDDDDDDDDDDDDD Timer 2 high F ------------CLSR C = Capture counter value for read (copy current counter value to $A/B $D/E) L = Enable Auto Reload Value (after counter value runs to 0 next value is $A/B $D/E) S = Stop timer R = Start timer (will do a Autoreload from $A/B $D/E) ----------------------------------------------------------- address = $8010 - $802F name = VIDEO read fedcba9876543210 10 00000DDDDDDDDDDD current HCount (11..0) 11 000000DDDDDDDDDD current VCount (10..0) 12 ---------------H Hit of programmed VCOUNT 13 ---------------- 14 ---------------- 15 ---------------- 16 ---------------- 17 ---------------- 18 ---------------- 19 ---------------- 1a ---------------- 1b ---------------- 1c ---------------- 1d ---------------- 1e ---------------- 1f ---------------- 20 ---------------- 21 ---------------- 22 ---------------- 23 ---------------- 24 ---------------- 25 ---------------- 26 ---------------- 27 ---------------- 28 ---------------- 29 ---------------- 2a ---------------- 2b ---------------- 2c ---------------- 2d ---------------- 2e ---------------- 2f ---------------- write fedcba9876543210 10 ---------------D VIDEO ON if '1' 11 ------DDDDDDDDDD HSYNC 12 ------DDDDDDDDDD HSTART 13 ------DDDDDDDDDD HMEMSTART 14 ------DDDDDDDDDD HSTOP 15 ------DDDDDDDDDD HTOTAL 16 -------DDDDDDDDD VSYNC 17 -------DDDDDDDDD VSTART 18 -------DDDDDDDDD VSTOP 19 -------DDDDDDDDD VTOTAL 1a DDDDDDDDDDDDDDDD LINE CACHE ADDRESS ADD LOW 1b DDDDDDDDDDDDDDDD LINE CACHE ADDRESS ADD HIGH 1c ---------------- LINE CACHE LATCH VALUE 1d -------DDDDDDDDD LINE CACHE START ADDRESS (Pixel offset) 1e --------DDDDDDDD HITVCOUNT (see description) 1f ---------------- 20 ------DDDDDDDDDD HLOADSTART 21 ------DDDDDDDDDD HLOADSTOP 22 -------DDDDDDDDD VLOADSTART 23 -------DDDDDDDDD VLOADSTOP 24 -------DDDDDDDDD VLOADNEXT 25 DDDDDDDDDDDDDDDD EXTERNAL MEMORY START ADDRESS (low) 26 DDDDDDDDDDDDDDDD EXTERNAL MEMORY START ADDRESS (high) 27 DDDDDDDDDDDDDDDD EXTERNAL MEMORY LINE OFFSET (low) 28 DDDDDDDDDDDDDDDD EXTERNAL MEMORY LINE OFFSET (high) 29 --------------DD MEMORY Convertion MODE 2a ---------------- LATCH MEMORY CONFIG 2b ---------------- 2c ---------------- 2d ---------------- 2e ---------------- 2f ---------------- HITVCOUNT = Programmable VCOUNT if this Value is written $12 bit 0 is set to '1' if VCOUNT is equal to this value $12 bit 0 is cleared at write to this register EXTERNAL MEMORY LINE OFFSET = will be add after every loaded line (for non interleaved video setup) MEMORY Convertion MODE = defines the format of data converted from external memory (ever 32Bit fetch) to line cache 00 = X8 R8 G8 B8 (32 Bit = (8 Bit for Red/Gree/Blue)) 01 = R5 R6 R5 R5 R6 R5 (2 * 16 Bit = (5 Bit for Red/Blue and 6 Bit for Green)) 10 = X1 R5 R5 X1 R5 R5 R5 R5 (2 * 16 Bit = (5 Bit for Red/Gree/Blue)) 11 = X4 R4 R4 R4 X4 R4 R4 R4 (2 * 16 Bit = (4 Bit for Red/Gree/Blue)) ----------------------------------------------------------- address = $8030 - $8031 name = PS/2 port a/b read fedcba9876543210 30 -----FWVDDDDDDDD port A 31 -----FWVDDDDDDDD port B D = PS/2 DATA (Scan Code) valid if A = '1' V = Data valid W = Write FIFO not full F = all writes finished (Fifo with 16 entries) note: wait 1 cycle after read/write request before read write fedcba9876543210 30 ------WADDDDDDDD port A 31 ------WADDDDDDDD port B D = PS/2 DATA to write A = get next scan code (read 2 cycles after this from $30/$31) W = Write data to PS/2 device ----------------------------------------------------------- address = $8032 - $8033 name = I2C port a/b read fedcba9876543210 30 ------------D--- port A (eeprom on DE2-115) 31 ------------D--- port B (audio/video in on DE2-115) D = data in from port A/B write fedcba9876543210 30 ----EEE------ICD port A 31 ----EEE------ICD port B D = data out value C = clock out value I = direction of data ('0' = in / '1' = out) EEE = is write enable for ICD ----------------------------------------------------------- address = $8034 - $803b name = AUDIO read fedcba9876543210 34 DDDDDDDDDDDDDDDD ADC data left high 35 --------DDDDDDDD ADC data left low 36 DDDDDDDDDDDDDDDD ADC data right high 37 --------DDDDDDDD ADC data right low 38 ---------------- 39 ---------------- 3a ---------------- 3b ---------------- write fedcba9876543210 fedcba9876543210 34 DDDDDDDDDDDDDDDD DAC data left high 35 --------DDDDDDDD DAC data left low 36 DDDDDDDDDDDDDDDD DAC data right high 37 --------DDDDDDDD DAC data right low 38 AAAAAAAADDDDDDDD ADAC Ctrl / Data 39 --------DDDDDDDD DAC interrupt generate if lower 3a --------DDDDDDDD ADC interrupt generate if higher 3b ---------------- ADC recive values (after 2 cycles available in $34-$37) ADAC Ctrl / Data = configure internal ADC/DAC controller Adr 76543210 0 -------- ignore 1 -------E enable DAC 2 ----CCCC DAC push counter (96KHz at 0, 48KHz at 1, 32KHz at 2 ....) 3 -------E enable ADC 4 ----CCCC ADC pull counter (96KHz at 0, 48KHz at 1, 32KHz at 2 ....) ----------------------------------------------------------- address = $803c - $8044 name = HCORE CTRL/IO (in experimental state)