library ieee; use work.bus_package.all; use work.hcore_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ucore_test_v2 is port ( -- CLOCK CLOCK_50 : in std_logic; CLOCK2_50 : in std_logic; CLOCK3_50 : in std_logic; -- Sma SMA_CLKIN : in std_logic; SMA_CLKOUT : out std_logic; -- LED LEDG : out std_logic_vector(8 downto 0); LEDR : out std_logic_vector(17 downto 0); -- KEY KEY : in std_logic_vector(3 downto 0); -- EJTAG EX_IO : inout std_logic_vector(6 downto 0); -- SW SW : in std_logic_vector(17 downto 0); -- SEG7 HEX0 : out std_logic_vector(6 downto 0); HEX1 : out std_logic_vector(6 downto 0); HEX2 : out std_logic_vector(6 downto 0); HEX3 : out std_logic_vector(6 downto 0); HEX4 : out std_logic_vector(6 downto 0); HEX5 : out std_logic_vector(6 downto 0); HEX6 : out std_logic_vector(6 downto 0); HEX7 : out std_logic_vector(6 downto 0); -- LCD LCD_BLON : out std_logic; LCD_DATA : inout std_logic_vector(7 downto 0); LCD_EN : out std_logic; LCD_ON : out std_logic; LCD_RS : out std_logic; LCD_RW : out std_logic; -- RS232 UART_CTS : out std_logic; UART_RTS : in std_logic; UART_RXD : in std_logic; UART_TXD : out std_logic; -- PS2 for Keyboard and Mouse PS2_CLK : inout std_logic; PS2_CLK2 : inout std_logic; PS2_DAT : inout std_logic; PS2_DAT2 : inout std_logic; -- SDCARD SD_CLK : out std_logic; SD_CMD : inout std_logic; SD_DAT : inout std_logic_vector(3 downto 0); SD_WP_N : in std_logic; -- VGA VGA_B : out std_logic_vector(7 downto 0); VGA_BLANK_N : out std_logic; VGA_CLK : out std_logic; VGA_G : out std_logic_vector(7 downto 0); VGA_HS : out std_logic; VGA_R : out std_logic_vector(7 downto 0); VGA_SYNC_N : out std_logic; VGA_VS : out std_logic; -- Audio AUD_ADCDAT : in std_logic; AUD_ADCLRCK : inout std_logic; AUD_BCLK : inout std_logic; AUD_DACDAT : out std_logic; AUD_DACLRCK : inout std_logic; AUD_XCK : out std_logic; -- I2C for EEPROM EEP_I2C_SCLK : out std_logic; EEP_I2C_SDAT : inout std_logic; -- I2C for Audio Tv-Decoder HSMC I2C_SCLK : out std_logic; I2C_SDAT : inout std_logic; -- Ethernet 0 ENET0_GTX_CLK : out std_logic; ENET0_INT_N : in std_logic; ENET0_LINK100 : in std_logic; ENET0_MDC : out std_logic; ENET0_MDIO : inout std_logic; ENET0_RST_N : out std_logic; ENET0_RX_CLK : in std_logic; ENET0_RX_COL : in std_logic; ENET0_RX_CRS : in std_logic; ENET0_RX_DATA : in std_logic_vector(3 downto 0); ENET0_RX_DV : in std_logic; ENET0_RX_ER : in std_logic; ENET0_TX_CLK : in std_logic; ENET0_TX_DATA : out std_logic_vector(3 downto 0); ENET0_TX_EN : out std_logic; ENET0_TX_ER : out std_logic; ENETCLK_25 : in std_logic; -- Ethernet 1 ENET1_GTX_CLK : out std_logic; ENET1_INT_N : in std_logic; ENET1_LINK100 : in std_logic; ENET1_MDC : out std_logic; ENET1_MDIO : inout std_logic; ENET1_RST_N : out std_logic; ENET1_RX_CLK : in std_logic; ENET1_RX_COL : in std_logic; ENET1_RX_CRS : in std_logic; ENET1_RX_DATA : in std_logic_vector(3 downto 0); ENET1_RX_DV : in std_logic; ENET1_RX_ER : in std_logic; ENET1_TX_CLK : in std_logic; ENET1_TX_DATA : out std_logic_vector(3 downto 0); ENET1_TX_EN : out std_logic; ENET1_TX_ER : out std_logic; -- TV Decoder TD_CLK27 : in std_logic; TD_DATA : in std_logic_vector(7 downto 0); TD_HS : in std_logic; TD_RESET_N : out std_logic; TD_VS : in std_logic; -- USB 2.0 OTG OTG_ADDR : out std_logic_vector(1 downto 0); OTG_CS_N : out std_logic; OTG_DACK_N : out std_logic_vector(1 downto 0); OTG_DATA : inout std_logic_vector(15 downto 0); OTG_DREQ : in std_logic_vector(1 downto 0); OTG_FSPEED : inout std_logic; OTG_INT : in std_logic_vector(1 downto 0); OTG_LSPEED : inout std_logic; OTG_RD_N : out std_logic; OTG_RST_N : out std_logic; OTG_WE_N : out std_logic; -- IR Receiver IRDA_RXD : in std_logic; -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(31 downto 0); DRAM_DQM : out std_logic_vector(3 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- SRAM SRAM_ADDR : out std_logic_vector(19 downto 0); SRAM_CE_N : out std_logic; SRAM_DQ : inout std_logic_vector(15 downto 0); SRAM_LB_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_WE_N : out std_logic; -- Flash FL_ADDR : out std_logic_vector(22 downto 0); FL_CE_N : out std_logic; FL_DQ : inout std_logic_vector(7 downto 0); FL_OE_N : out std_logic; FL_RST_N : out std_logic; FL_RY : in std_logic; FL_WE_N : out std_logic; FL_WP_N : out std_logic; -- GPIO, GPIO connect to GPIO Default GPIO : inout std_logic_vector(35 downto 0); -- HSMC, HSMC connect to HSMC Default HSMC_CLKIN_N1 : in std_logic; HSMC_CLKIN_N2 : in std_logic; HSMC_CLKIN_P1 : in std_logic; HSMC_CLKIN_P2 : in std_logic; HSMC_CLKIN0 : in std_logic; HSMC_CLKOUT_N1 : out std_logic; HSMC_CLKOUT_N2 : out std_logic; HSMC_CLKOUT_P1 : out std_logic; HSMC_CLKOUT_P2 : out std_logic; HSMC_CLKOUT0 : out std_logic; HSMC_D : inout std_logic_vector(3 downto 0); HSMC_RX_D_N : inout std_logic_vector(16 downto 0); HSMC_RX_D_P : inout std_logic_vector(16 downto 0); HSMC_TX_D_N : inout std_logic_vector(16 downto 0); HSMC_TX_D_P : inout std_logic_vector(16 downto 0) ); end entity; architecture rtl of ucore_test_v2 is -- plls component pll_system PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC; c1 : OUT STD_LOGIC; locked : OUT STD_LOGIC ); end component; signal pll_system_locked : std_logic := '0'; component pll_sdram PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC; c1 : OUT STD_LOGIC; locked : OUT STD_LOGIC ); end component; signal pll_sdram_locked : std_logic := '0'; component pll_video PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); end component; signal pll_video_locked : std_logic := '0'; -- oddr component oddr is port ( datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0); outclock : IN STD_LOGIC ; dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); end component; signal sdram_clk3ns_dataout : STD_LOGIC_VECTOR (0 DOWNTO 0) := (others =>'0'); signal audio_clk_dataout : STD_LOGIC_VECTOR (0 DOWNTO 0) := (others =>'0'); -- flash component mem_flash is port ( -- global clk : in std_logic; reset : in std_logic; -- Flash FL_ADDR : out std_logic_vector(22 downto 0); FL_CE_N : out std_logic; FL_DQ : inout std_logic_vector(7 downto 0); FL_OE_N : out std_logic; FL_RST_N : out std_logic; FL_RY : in std_logic; FL_WE_N : out std_logic; FL_WP_N : out std_logic; -- recive ports to_flash_data : in flash_n_data_t; to_flash_busy : in flash_n_busy_t; to_flash_ack : out flash_n_ack_t; -- send ports from_flash_rclk : in flash_rclk_t; from_flash_data : out flash_n_data_t; from_flash_busy : out flash_n_busy_t; from_flash_ack : in flash_n_ack_t ); end component; signal to_flash_data : flash_n_data_t := (others => (others => '0')); signal to_flash_busy : flash_n_busy_t := (others => ('0')); signal to_flash_ack : flash_n_ack_t := (others => ('0')); signal from_flash_rclk : flash_rclk_t := (others => ('0')); signal from_flash_data : flash_n_data_t := (others => (others => '0')); signal from_flash_busy : flash_n_busy_t := (others => ('0')); signal from_flash_ack : flash_n_ack_t := (others => ('0')); -- sram component mem_sram is port ( -- global clk : in std_logic; reset : in std_logic; -- SRAM SRAM_ADDR : out std_logic_vector(19 downto 0); SRAM_CE_N : out std_logic; SRAM_DQ : inout std_logic_vector(15 downto 0); SRAM_LB_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_WE_N : out std_logic; -- recive ports to_sram_data : in sram_n_data_t; to_sram_busy : in sram_n_busy_t; to_sram_ack : out sram_n_ack_t; -- send ports from_sram_rclk : in sram_rclk_t; from_sram_data : out sram_n_data_t; from_sram_busy : out sram_n_busy_t; from_sram_ack : in sram_n_ack_t ); end component; signal to_sram_data : sram_n_data_t := (others => (others => '0')); signal to_sram_busy : sram_n_busy_t := (others => ('0')); signal to_sram_ack : sram_n_ack_t := (others => ('0')); signal from_sram_rclk : sram_rclk_t; signal from_sram_data : sram_n_data_t := (others => (others => '0')); signal from_sram_busy : sram_n_busy_t := (others => ('0')); signal from_sram_ack : sram_n_ack_t := (others => ('0')); -- dram component mem_sdram is port ( -- global clk : in std_logic; reset : in std_logic; -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(31 downto 0); DRAM_DQM : out std_logic_vector(3 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- recive ports to_sdram_data : in sdram_n_data_t; to_sdram_busy : in sdram_n_busy_t; to_sdram_ack : out sdram_n_ack_t; -- send ports from_sdram_rclk : in sdram_rclk_t; from_sdram_data : out sdram_n_data_t; from_sdram_busy : out sdram_n_busy_t; from_sdram_ack : in sdram_n_ack_t ); end component; component mem_sdram_MODELSIM is port ( -- global clk : in std_logic; reset : in std_logic; -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(31 downto 0); DRAM_DQM : out std_logic_vector(3 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- recive ports to_sdram_data : in sdram_n_data_t; to_sdram_busy : in sdram_n_busy_t; to_sdram_ack : out sdram_n_ack_t; -- send ports from_sdram_rclk : in sdram_rclk_t; from_sdram_data : out sdram_n_data_t; from_sdram_busy : out sdram_n_busy_t; from_sdram_ack : in sdram_n_ack_t ); end component; signal to_sdram_data : sdram_n_data_t := (others => (others => '0')); signal to_sdram_busy : sdram_n_busy_t := (others => ('0')); signal to_sdram_ack : sdram_n_ack_t := (others => ('0')); -- send ports signal from_sdram_rclk : sdram_rclk_t := (others => ('0')); signal from_sdram_data : sdram_n_data_t := (others => (others => '0')); signal from_sdram_busy : sdram_n_busy_t := (others => ('0')); signal from_sdram_ack : sdram_n_ack_t := (others => ('0')); -- sd card ctrl component sdCtrl is port ( -- global clk : in std_logic; reset : in std_logic; -- SDCARD SD_CLK : out std_logic; SD_CMD : inout std_logic; SD_DAT : inout std_logic_vector(3 downto 0); SD_WP_N : in std_logic; -- external -- ctrl port -- send ctrl_send_data : out std_logic_vector(15 downto 0); ctrl_send_address : out std_logic_vector(31 downto 0); ctrl_send_we : out std_logic; ctrl_send_busy : in std_logic; ctrl_send_wrreq : out std_logic; -- recive ctrl_recive_data : in std_logic_vector(15 downto 0); ctrl_recive_address : in std_logic_vector(31 downto 0); ctrl_recive_we : in std_logic; ctrl_recive_busy : in std_logic; ctrl_recive_ack : out std_logic; -- data port -- send data_send_data : out std_logic_vector(15 downto 0); data_send_address : out std_logic_vector(31 downto 0); data_send_we : out std_logic; data_send_busy : in std_logic; data_send_wrreq : out std_logic ); end component; signal sd_ctrl_send_data : std_logic_vector(15 downto 0) := (others => '0'); signal sd_ctrl_send_address : std_logic_vector(31 downto 0) := (others => '0'); signal sd_ctrl_send_we : std_logic := '0'; signal sd_ctrl_send_busy : std_logic := '1'; signal sd_ctrl_send_wrreq : std_logic := '0'; signal sd_ctrl_recive_data : std_logic_vector(15 downto 0) := (others => '0'); signal sd_ctrl_recive_address : std_logic_vector(31 downto 0) := (others => '0'); signal sd_ctrl_recive_we : std_logic := '0'; signal sd_ctrl_recive_busy : std_logic := '1'; signal sd_ctrl_recive_ack : std_logic := '0'; signal sd_data_send_data : std_logic_vector(15 downto 0) := (others => '0'); signal sd_data_send_address : std_logic_vector(31 downto 0) := (others => '0'); signal sd_data_send_we : std_logic := '0'; signal sd_data_send_busy : std_logic := '1'; signal sd_data_send_wrreq : std_logic := '0'; -- component bus_arbiter_sd_card is port ( -- global clk : in std_logic; reset : in std_logic; -- sd card -- ctrl port -- send ctrl_send_data : in std_logic_vector(15 downto 0); ctrl_send_address : in std_logic_vector(31 downto 0); ctrl_send_we : in std_logic; ctrl_send_busy : out std_logic; ctrl_send_wrreq : in std_logic; -- recive ctrl_recive_data : out std_logic_vector(15 downto 0); ctrl_recive_address : out std_logic_vector(31 downto 0); ctrl_recive_we : out std_logic; ctrl_recive_busy : out std_logic; ctrl_recive_ack : in std_logic; -- memory clks sram_clk : in std_logic; sdram_clk : in std_logic; ctrl_clk : in std_logic; -- data port -- send data_send_data : in std_logic_vector(15 downto 0); data_send_address : in std_logic_vector(31 downto 0); data_send_we : in std_logic; data_send_busy : out std_logic; data_send_wrreq : in std_logic; -- external bus -- data -- to memory (DATA PORT) data_to_sram_data : out std_logic_vector(71 downto 0); data_to_sram_busy : out std_logic; data_to_sram_ack : in std_logic; data_to_sdram_data : out std_logic_vector(71 downto 0); data_to_sdram_busy : out std_logic; data_to_sdram_ack : in std_logic; -- ctrl -- to memory -- recive ports ctrl_to_sd_data : in sd_ctrl_n_data_t; ctrl_to_sd_busy : in sd_ctrl_n_busy_t; ctrl_to_sd_ack : out sd_ctrl_n_ack_t; -- from memory fifos ctrl_from_sd_data : out sd_ctrl_n_data_t; ctrl_from_sd_busy : out sd_ctrl_n_busy_t; ctrl_from_sd_ack : in sd_ctrl_n_ack_t ); end component; -- ports signal ctrl_to_sd_data : sd_ctrl_n_data_t := (others => (others => '0')); signal ctrl_to_sd_busy : sd_ctrl_n_busy_t := (others => ('0')); signal ctrl_to_sd_ack : sd_ctrl_n_ack_t := (others => ('0')); signal ctrl_from_sd_data : sd_ctrl_n_data_t := (others => (others => '0')); signal ctrl_from_sd_busy : sd_ctrl_n_busy_t := (others => ('0')); signal ctrl_from_sd_ack : sd_ctrl_n_ack_t := (others => ('0')); -- ucore component ucore is port ( -- global clk : in std_logic; reset : in std_logic; -- irq : in std_logic; -- ctrl port ctrl_port_a_adress : out std_logic_vector(6 downto 0); ctrl_port_a_q : in std_logic_vector(15 downto 0); ctrl_port_a_data : out std_logic_vector(15 downto 0); ctrl_port_a_we : out std_logic; -- external -- send ext_send_data : out std_logic_vector(15 downto 0); ext_send_address : out std_logic_vector(31 downto 0); ext_send_we : out std_logic; ext_send_busy : in std_logic; ext_send_wrreq : out std_logic; -- recive ext_recive_data : in std_logic_vector(15 downto 0); ext_recive_busy : in std_logic; ext_recive_ack : out std_logic; -- diag stall_out : out std_logic ); end component; signal ucore1_ext_send_data32 : std_logic_vector(31 downto 0) := (others => '0'); signal ucore1_ext_send_data : std_logic_vector(15 downto 0) := (others => '0'); signal ucore1_ext_send_address : std_logic_vector(31 downto 0) := (others => '0'); signal ucore1_ext_send_we : std_logic := '0'; signal ucore1_ext_send_busy : std_logic := '0'; signal ucore1_ext_send_wrreq : std_logic := '0'; signal ucore1_ext_recive_data : std_logic_vector(15 downto 0) := (others => '0'); signal ucore1_ext_recive_busy : std_logic := '0'; signal ucore1_ext_recive_ack : std_logic := '0'; -- ucore arbiter component bus_arbiter_ucore is port ( -- global clk : in std_logic; reset : in std_logic; -- ucore1 -- send ucore_send_data : in std_logic_vector(31 downto 0); ucore_send_address : in std_logic_vector(31 downto 0); ucore_send_we : in std_logic; ucore_send_dmode : in std_logic; ucore_send_busy : out std_logic; ucore_send_wrreq : in std_logic; -- recive ucore_recive_data : out std_logic_vector(15 downto 0); ucore_recive_busy : out std_logic; ucore_recive_ack : in std_logic; -- memory clks sram_clk : in std_logic; flash_clk : in std_logic; sdram_clk : in std_logic; sdctrl_clk : in std_logic; -- to memory to_sram_data : out std_logic_vector(71 downto 0); to_sram_busy : out std_logic; to_sram_ack : in std_logic; to_flash_data : out std_logic_vector(71 downto 0); to_flash_busy : out std_logic; to_flash_ack : in std_logic; to_sdram_data : out std_logic_vector(71 downto 0); to_sdram_busy : out std_logic; to_sdram_ack : in std_logic; to_sdctrl_data : out std_logic_vector(71 downto 0); to_sdctrl_busy : out std_logic; to_sdctrl_ack : in std_logic; -- from memory fifos from_sram_data : in std_logic_vector(71 downto 0); from_sram_busy : in std_logic; from_sram_ack : out std_logic; from_flash_data : in std_logic_vector(71 downto 0); from_flash_busy : in std_logic; from_flash_ack : out std_logic; from_sdram_data : in std_logic_vector(71 downto 0); from_sdram_busy : in std_logic; from_sdram_ack : out std_logic; from_sdctrl_data : in std_logic_vector(71 downto 0); from_sdctrl_busy : in std_logic; from_sdctrl_ack : out std_logic ); end component; -- uctrl component utility_ctrl is port ( -- clk : in std_logic; reset : in std_logic; clk_audio : in std_logic; reset_audio : in std_logic; reset_fall_audio : in std_logic; -- utility core port ctrl_port_a_adress : in std_logic_vector(6 downto 0); ctrl_port_a_q : out std_logic_vector(15 downto 0); ctrl_port_a_data : in std_logic_vector(15 downto 0); ctrl_port_a_we : in std_logic; -- irq_out : out std_logic; -- hcore hcore_clk : in std_logic; hcore_data : out hcore_ctrl_struct_t; hcore_busy : out std_logic; hcore_ack : in std_logic; -- from hcores i_from_hcores_data : in hcore_to_uctrl_struct_t; i_from_hcores_empty : in std_logic; o_from_hcores_rdreq : out std_logic; -- to hcores o_to_hcores_data : out uctrl_to_hcore_struct_t; o_to_hcores_empty : out std_logic; i_to_hcores_rdreq : in std_logic; -- SW SW : in std_logic_vector(15 downto 0); -- SEG7 HEX0 : out std_logic_vector(6 downto 0); HEX1 : out std_logic_vector(6 downto 0); HEX2 : out std_logic_vector(6 downto 0); HEX3 : out std_logic_vector(6 downto 0); HEX4 : out std_logic_vector(6 downto 0); HEX5 : out std_logic_vector(6 downto 0); HEX6 : out std_logic_vector(6 downto 0); HEX7 : out std_logic_vector(6 downto 0); -- LED LEDG : out std_logic_vector(8 downto 0); LEDR : out std_logic_vector(8 downto 0); -- LCD LCD_BLON : out std_logic; LCD_DATA : inout std_logic_vector(7 downto 0); LCD_EN : out std_logic; LCD_ON : out std_logic; LCD_RS : out std_logic; LCD_RW : out std_logic; -- VGA VGA_B : out std_logic_vector(7 downto 0); VGA_BLANK_N : out std_logic; VGA_CLK : out std_logic; VGA_G : out std_logic_vector(7 downto 0); VGA_HS : out std_logic; VGA_R : out std_logic_vector(7 downto 0); VGA_SYNC_N : out std_logic; VGA_VS : out std_logic; --PS2 PS2_CLK : inout std_logic; PS2_CLK2 : inout std_logic; PS2_DAT : inout std_logic; PS2_DAT2 : inout std_logic; -- I2C for EEPROM EEP_I2C_SCLK : out std_logic; EEP_I2C_SDAT : inout std_logic; -- I2C for Audio Tv-Decoder HSMC I2C_SCLK : out std_logic; I2C_SDAT : inout std_logic; -- AUDIO AUD_ADCDAT : in std_logic; AUD_ADCLRCK : inout std_logic; AUD_DACDAT : out std_logic; AUD_DACLRCK : inout std_logic; -- external -- send ext_send_address : out std_logic_vector(31 downto 0); ext_send_busy : in std_logic; ext_send_wrreq : out std_logic; -- recive ext_recive_data : in std_logic_vector(31 downto 0); ext_recive_busy : in std_logic; ext_recive_ack : out std_logic; -- errors error_audio_dac_no_data : out std_logic; error_audio_dac_full : out std_logic; error_audio_adc_no_data : out std_logic; error_audio_adc_full : out std_logic ); end component; signal to_hcores_data : uctrl_to_hcore_struct_t := raw_to_from_uctrl((others => '0')); signal to_hcores_empty : std_logic := '0'; signal to_hcores_rdreq : std_logic := '0'; signal video_ext_send_address : std_logic_vector(31 downto 0) := (others => '0'); signal video_ext_send_busy : std_logic := '0'; signal video_ext_send_wrreq : std_logic := '0'; signal video_ext_recive_data : std_logic_vector(31 downto 0) := (others => '0'); signal video_ext_recive_busy : std_logic := '0'; signal video_ext_recive_ack : std_logic := '0'; -- uctrl bus arbiter component bus_arbiter_uctrl is port ( -- global clk : in std_logic; reset : in std_logic; -- uctrl -- send uctrl_send_address : in std_logic_vector(31 downto 0); uctrl_send_busy : out std_logic; uctrl_send_wrreq : in std_logic; -- recive uctrl_recive_data : out std_logic_vector(31 downto 0); uctrl_recive_busy : out std_logic; uctrl_recive_ack : in std_logic; -- memory clks sram_clk : in std_logic; sdram_clk : in std_logic; -- to memory to_sram_data : out std_logic_vector(71 downto 0); to_sram_busy : out std_logic; to_sram_ack : in std_logic; to_sdram_data : out std_logic_vector(71 downto 0); to_sdram_busy : out std_logic; to_sdram_ack : in std_logic; -- from memory fifos from_sram_data : in std_logic_vector(71 downto 0); from_sram_busy : in std_logic; from_sram_ack : out std_logic; from_sdram_data : in std_logic_vector(71 downto 0); from_sdram_busy : in std_logic; from_sdram_ack : out std_logic ); end component; -- signal ctrl_port_a_adress : std_logic_vector(6 downto 0) := (others => '0'); signal ctrl_port_a_q : std_logic_vector(15 downto 0) := (others => '0'); signal ctrl_port_a_data : std_logic_vector(15 downto 0) := (others => '0'); signal ctrl_port_a_we : std_logic := '0'; signal ctrl_irq_out : std_logic := '0'; signal error_audio_dac_no_data : std_logic := '0'; signal error_audio_dac_full : std_logic := '0'; signal error_audio_adc_no_data : std_logic := '0'; signal error_audio_adc_full : std_logic := '0'; -- hcores component hcores is port ( -- global clk : in std_logic; reset : in std_logic; -- uctrl in hcore_data : in hcore_ctrl_struct_t; hcore_busy : in std_logic; hcore_ack : out std_logic; -- to uctrl i_to_hctrl_clk : in std_logic; o_to_hctrl_data : out hcore_to_uctrl_struct_t; o_to_hctrl_empty : out std_logic; i_to_hctrl_rdreq : in std_logic; -- from uctrl i_from_uctrl_data : in uctrl_to_hcore_struct_t; i_from_uctrl_empty : in std_logic; o_from_uctrl_rdreq : out std_logic; -- stall out stalls : out std_logic_vector(15 downto 0); -- memory clks sdram_clk : in std_logic; -- INST -- to memory inst_to_sdram_data : out std_logic_vector(71 downto 0); inst_to_sdram_busy : out std_logic; inst_to_sdram_ack : in std_logic; -- from memory fifos inst_from_sdram_data : in std_logic_vector(71 downto 0); inst_from_sdram_busy : in std_logic; inst_from_sdram_ack : out std_logic; -- DATA -- to memory data_to_sdram_data : out std_logic_vector(71 downto 0); data_to_sdram_busy : out std_logic; data_to_sdram_ack : in std_logic; -- from memory fifos data_from_sdram_data : in std_logic_vector(71 downto 0); data_from_sdram_busy : in std_logic; data_from_sdram_ack : out std_logic ); end component; signal to_hctrl_clk : std_logic := '0'; signal to_hctrl_data : hcore_to_uctrl_struct_t := raw_to_to_uctrl((others => '0')); signal to_hctrl_empty : std_logic := '0'; signal to_hctrl_rdreq : std_logic := '0'; -- signal clk_video : std_logic := '0'; signal clk_audio : std_logic := '0'; signal clk_100Mhz : std_logic := '0'; signal clk_sdram : std_logic := '0'; signal clk_sdram_m3ns : std_logic := '0'; signal clk_hcores : std_logic := '0'; signal reset_video : std_logic := '1'; signal reset_audio : std_logic := '1'; signal reset_fall_audio : std_logic := '1'; signal reset_100Mhz : std_logic := '1'; signal reset_sdram : std_logic := '1'; signal reset_hcores : std_logic := '1'; signal external_rest_video : std_logic := '1'; signal external_reset_100Mhz : std_logic := '1'; signal external_reset_sdram : std_logic := '1'; signal external_reset_audio : std_logic := '1'; signal external_reset_fall_audio : std_logic := '1'; signal external_irq_video : std_logic := '1'; signal external_reset_hcores : std_logic := '1'; signal ut_irq : std_logic := '0'; -- ucore1 signal ucore1_stall : std_logic := '0'; signal led_status : std_logic_vector(7 downto 0) := (others => '0'); signal led_status_audio : std_logic := '0'; -- SD signal SD_CLK_OUT : std_logic := '0'; -- I2C signal EEP_I2C_SCLK_OUT : std_logic := '0'; signal I2C_SCLK_OUT : std_logic := '0'; -- audio signal AUD_DACDAT_OUT : std_logic := '0'; signal AUD_DACLRCK_OUT : std_logic := '0'; constant MODELSIM : boolean := false -- synthesis translate_off or true -- synthesis translate_on ; signal SW_buffer : std_logic_vector(17 downto 0) := (others => '0'); signal plls_locked : std_logic := '0'; signal debug : std_logic_vector(1 downto 0) := (others => '0'); -- hcore signal hcore_data : hcore_ctrl_struct_t := (others => (others =>'0')); signal hcore_busy : std_logic := '0'; signal hcore_ack : std_logic := '0'; signal hcore_stalls : std_logic_vector(15 downto 0) := (others => '0'); begin -- plls (without modelsim) pll_block: if MODELSIM = false generate cgen_100Mhz : pll_system port map ( CLOCK_50, clk_100Mhz, clk_hcores, pll_system_locked ); cgen_sdram : pll_sdram port map ( CLOCK_50, clk_sdram, clk_sdram_m3ns, pll_sdram_locked ); cgen_ucore_uctrl_and_audio : pll_video port map ( CLOCK2_50, clk_video, clk_audio, pll_video_locked ); end generate; -- pll (modelsim) pll_block_ms: if MODELSIM = true generate clk_100Mhz <= CLOCK_50; clk_hcores <= CLOCK_50; clk_sdram <= CLOCK2_50; clk_sdram_m3ns <= CLOCK2_50; clk_video <= CLOCK_50; clk_audio <= CLOCK_50; pll_system_locked <= '1'; pll_sdram_locked <= '1'; pll_video_locked <= '1'; end generate; -- plls_locked <= pll_system_locked and pll_sdram_locked and pll_video_locked; -- external clks -- ext_dram_clk_3ns : oddr port map -- ( -- "1", -- "0", -- clk_sdram_m3ns, -- 3n shift -- sdram_clk3ns_dataout -- ); DRAM_CLK <= clk_sdram_m3ns;--clk_sdram;--sdram_clk3ns_dataout(0); SD_CLK <= SD_CLK_OUT; EEP_I2C_SCLK <= EEP_I2C_SCLK_OUT; I2C_SCLK <= I2C_SCLK_OUT; AUD_DACDAT <= AUD_DACDAT_OUT; AUD_DACLRCK <= AUD_DACLRCK_OUT; AUD_BCLK <= clk_audio; AUD_XCK <= clk_audio; -- diag process(clk_audio) begin if rising_edge(clk_audio) then led_status_audio <= error_audio_dac_no_data; LEDR(9) <= led_status_audio; end if; end process; process(clk_video) begin if rising_edge(clk_video) then -- led (config by SW 17 & SW 16) case SW_buffer(17 downto 16) is when "00" => led_status <= ucore1_stall & (not PS2_DAT) & (not PS2_DAT2) & error_audio_dac_full & "0000"; when others => led_status <= (others => '0'); end case; -- LEDR(17 downto 10) <= led_status; ------ debug to GPIO debug(0) <= IRDA_RXD; debug(1) <= '0';--I2C_SDAT; GPIO(0) <= debug(0); GPIO(1) <= debug(1); end if; end process; --hcore_stalls -- sync reset / irq test process(clk_video) begin if rising_edge(clk_video) then external_rest_video <= not KEY(0) or not plls_locked; external_irq_video <= not KEY(1); reset_video <= external_rest_video; SW_buffer <= SW; end if; end process; process(clk_100Mhz) begin if rising_edge(clk_100Mhz) then external_reset_100Mhz <= not KEY(0) or not plls_locked; reset_100Mhz <= external_reset_100Mhz; end if; end process; process(clk_sdram) begin if rising_edge(clk_sdram) then external_reset_sdram <= not KEY(0) or not plls_locked; reset_sdram <= external_reset_sdram; end if; end process; process(clk_audio) begin if rising_edge(clk_audio) then external_reset_audio <= not KEY(0) or not plls_locked; reset_audio <= external_reset_audio; end if; end process; process(clk_audio) begin if falling_edge(clk_audio) then external_reset_fall_audio <= not KEY(0) or not plls_locked; reset_fall_audio <= external_reset_fall_audio; end if; end process; process(clk_hcores) begin if rising_edge(clk_hcores) then external_reset_hcores <= not KEY(0) or not plls_locked; reset_hcores <= external_reset_hcores; end if; end process; -- flash ext_mem_flash : mem_flash port map ( clk_100Mhz, reset_100Mhz, FL_ADDR, FL_CE_N, FL_DQ, FL_OE_N, FL_RST_N, FL_RY, FL_WE_N, FL_WP_N, to_flash_data, to_flash_busy, to_flash_ack, from_flash_rclk, from_flash_data, from_flash_busy, from_flash_ack ); from_flash_rclk(0) <= clk_video; -- port 0 is uctrl -- sram ext_mem_sram : mem_sram port map ( clk_100Mhz, reset_100Mhz, SRAM_ADDR, SRAM_CE_N, SRAM_DQ, SRAM_LB_N, SRAM_OE_N, SRAM_UB_N, SRAM_WE_N, to_sram_data, to_sram_busy, to_sram_ack , from_sram_rclk, from_sram_data, from_sram_busy, from_sram_ack ); from_sram_rclk(0) <= clk_video; -- port 0 is uctrl from_sram_rclk(1) <= clk_video; -- port 1 is ucore -- sdram -- normal sdram_hard: if MODELSIM = false generate ext_mem_sdram : mem_sdram port map ( clk_sdram, reset_sdram, DRAM_ADDR, DRAM_BA, DRAM_CAS_N, DRAM_CS_N, DRAM_DQ, DRAM_DQM, DRAM_RAS_N, DRAM_WE_N, to_sdram_data, to_sdram_busy, to_sdram_ack, from_sdram_rclk, from_sdram_data, from_sdram_busy, from_sdram_ack ); end generate; -- modelsim sdram_modelsim: if MODELSIM = true generate ext_mem_sdram : mem_sdram_MODELSIM port map ( clk_sdram, reset_sdram, DRAM_ADDR, DRAM_BA, DRAM_CAS_N, DRAM_CS_N, DRAM_DQ, DRAM_DQM, DRAM_RAS_N, DRAM_WE_N, to_sdram_data, to_sdram_busy, to_sdram_ack, from_sdram_rclk, from_sdram_data, from_sdram_busy, from_sdram_ack ); end generate; from_sdram_rclk(0) <= clk_video; -- port 0 is uctrl from_sdram_rclk(1) <= clk_video; -- port 1 is ucore from_sdram_rclk(3) <= clk_hcores; -- port 3 is hcore from_sdram_rclk(4) <= clk_hcores; -- port 4 is hcore -- sd ext_sdCard : sdCtrl port map ( clk_100Mhz, reset_100Mhz, SD_CLK_OUT, SD_CMD, SD_DAT, SD_WP_N, sd_ctrl_send_data, sd_ctrl_send_address, sd_ctrl_send_we, sd_ctrl_send_busy, sd_ctrl_send_wrreq, sd_ctrl_recive_data, sd_ctrl_recive_address, sd_ctrl_recive_we, sd_ctrl_recive_busy, sd_ctrl_recive_ack, sd_data_send_data, sd_data_send_address, sd_data_send_we, sd_data_send_busy, sd_data_send_wrreq ); sd_card_bus_arb : bus_arbiter_sd_card port map ( clk_100Mhz, reset_100Mhz, sd_ctrl_send_data, sd_ctrl_send_address, sd_ctrl_send_we, sd_ctrl_send_busy, sd_ctrl_send_wrreq, sd_ctrl_recive_data, sd_ctrl_recive_address, sd_ctrl_recive_we, sd_ctrl_recive_busy, sd_ctrl_recive_ack, clk_100Mhz, clk_sdram, clk_video, sd_data_send_data, sd_data_send_address, sd_data_send_we, sd_data_send_busy, sd_data_send_wrreq, to_sram_data(2), -- sram port 1 to_sram_busy(2), to_sram_ack(2), to_sdram_data(2), -- dram port 1 to_sdram_busy(2), to_sdram_ack(2), ctrl_to_sd_data, ctrl_to_sd_busy, ctrl_to_sd_ack, ctrl_from_sd_data, ctrl_from_sd_busy, ctrl_from_sd_ack ); -- to sram/sdram ports are only write from_sram_busy(2) <= '1'; from_sdram_busy(2) <= '1'; from_sram_rclk(2) <= clk_100Mhz; from_sdram_rclk(2) <= clk_100Mhz; from_sram_ack(2) <= '0'; from_sdram_ack(2) <= '0'; -- ucore ut_irq <= external_irq_video or ctrl_irq_out; -- irq by key or ctrl ucore_v2 : ucore port map ( clk_video, reset_video, ut_irq, ctrl_port_a_adress, ctrl_port_a_q, ctrl_port_a_data, ctrl_port_a_we, ucore1_ext_send_data, ucore1_ext_send_address, ucore1_ext_send_we, ucore1_ext_send_busy, ucore1_ext_send_wrreq, ucore1_ext_recive_data, ucore1_ext_recive_busy, ucore1_ext_recive_ack, ucore1_stall ); -- ucore bus arbiter ucore1_ext_send_data32 <= x"0000" & ucore1_ext_send_data; ucore_bus_arbiter : bus_arbiter_ucore port map ( clk_video, reset_video, ucore1_ext_send_data32, -- 16 bit data ucore1_ext_send_address, ucore1_ext_send_we, '1', -- 16 bit (dmode = '1') ucore1_ext_send_busy, ucore1_ext_send_wrreq, ucore1_ext_recive_data, ucore1_ext_recive_busy, ucore1_ext_recive_ack, clk_100Mhz, -- sram clk clk_100Mhz, -- flash clk clk_sdram, -- sdram clk clk_100Mhz, -- sd card clk to_sram_data(1), -- sram port 1 to_sram_busy(1), to_sram_ack(1), to_flash_data(0), -- flash port 0 to_flash_busy(0), to_flash_ack(0), to_sdram_data(1), -- sdram port 1 to_sdram_busy(1), to_sdram_ack(1), ctrl_to_sd_data(0), ctrl_to_sd_busy(0), ctrl_to_sd_ack(0), from_sram_data(1), -- sram port 1 from_sram_busy(1), from_sram_ack(1), from_flash_data(0), -- flash port 0 from_flash_busy(0), from_flash_ack(0), from_sdram_data(1), -- sdram port 1 from_sdram_busy(1), from_sdram_ack(1), ctrl_from_sd_data(0), ctrl_from_sd_busy(0), ctrl_from_sd_ack(0) ); -- ucore ctrl port uctrl : utility_ctrl port map ( clk_video, -- clk like ucore 1 reset_video, clk_audio, -- audio clk reset_audio, reset_fall_audio, ctrl_port_a_adress, ctrl_port_a_q, ctrl_port_a_data, ctrl_port_a_we, ctrl_irq_out, clk_hcores, hcore_data, hcore_busy, hcore_ack, to_hctrl_data, to_hctrl_empty, to_hctrl_rdreq, to_hcores_data, to_hcores_empty, to_hcores_rdreq, SW_buffer(15 downto 0), HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, LEDG, LEDR(8 downto 0), LCD_BLON, LCD_DATA, LCD_EN, LCD_ON, LCD_RS, LCD_RW, VGA_B, VGA_BLANK_N, VGA_CLK, VGA_G, VGA_HS, VGA_R, VGA_SYNC_N, VGA_VS, PS2_CLK, PS2_CLK2, PS2_DAT, PS2_DAT2, EEP_I2C_SCLK_OUT, EEP_I2C_SDAT, I2C_SCLK_OUT, I2C_SDAT, AUD_ADCDAT, AUD_ADCLRCK, AUD_DACDAT_OUT, AUD_DACLRCK_OUT, video_ext_send_address, video_ext_send_busy, video_ext_send_wrreq, video_ext_recive_data, video_ext_recive_busy, video_ext_recive_ack, error_audio_dac_no_data, error_audio_dac_full, error_audio_adc_no_data, error_audio_adc_full ); -- uctrl bus aribter uctrl_bus_arbiter : bus_arbiter_uctrl port map ( clk_video, reset_video, video_ext_send_address, video_ext_send_busy, video_ext_send_wrreq, video_ext_recive_data, video_ext_recive_busy, video_ext_recive_ack, clk_100Mhz, -- sram clk clk_sdram, -- sdram clk to_sram_data(0), -- sram port 0 to_sram_busy(0), to_sram_ack(0), to_sdram_data(0), -- sdram port 0 to_sdram_busy(0), to_sdram_ack(0), from_sram_data(0), -- sram port 0 from_sram_busy(0), from_sram_ack(0), from_sdram_data(0), -- sdram port 0 from_sdram_busy(0), from_sdram_ack(0) ); DRAM_CKE <= '1'; -- on -- hcores to_hctrl_clk <= clk_video; hcores_block : hcores port map ( clk_hcores, reset_hcores, hcore_data, hcore_busy, hcore_ack, to_hctrl_clk, to_hctrl_data, to_hctrl_empty, to_hctrl_rdreq, to_hcores_data, to_hcores_empty, to_hcores_rdreq, hcore_stalls, clk_sdram, to_sdram_data(3), -- inst to_sdram_busy(3), to_sdram_ack(3), from_sdram_data(3), from_sdram_busy(3), from_sdram_ack(3), to_sdram_data(4), -- data to_sdram_busy(4), to_sdram_ack(4), from_sdram_data(4), from_sdram_busy(4), from_sdram_ack(4) ); -- unused parts -- Sma SMA_CLKOUT <= '0'; -- RS232 UART_CTS <= '0'; UART_TXD <= '0'; -- Ethernet 0 ENET0_RST_N <= '1'; -- Ethernet 1 ENET1_RST_N <= '1'; -- TV Decoder TD_RESET_N <= '1'; -- USB 2.0 OTG OTG_CS_N <= '1'; OTG_RST_N <= '1'; -- GPIO, GPIO connect to GPIO Default GPIO(35 downto 2) <= (others =>'0'); -- HSMC, HSMC connect to HSMC Default HSMC_CLKOUT_N1 <= '0'; HSMC_CLKOUT_N2 <= '0'; HSMC_CLKOUT_P1 <= '0'; HSMC_CLKOUT_P2 <= '0'; HSMC_CLKOUT0 <= '0'; HSMC_D <= (others =>'0'); HSMC_RX_D_N <= (others =>'0'); HSMC_RX_D_P <= (others =>'0'); HSMC_TX_D_N <= (others =>'0'); HSMC_TX_D_P <= (others =>'0'); end rtl;